1. Field of the Invention
The present invention relates to a multi-level power supply, and more particularly, to a technique of managing a multi-level power supply to avoid a latch-up of a complementary metal oxide semiconductor (CMOS) circuit.
2. Description of the Related Art
A semiconductor integrated circuit may include numerous active and passive devices. For example, the circuit may include active devices such as transistors, diodes, and thyristors, and passive devices such as capacitors, resistors and inductors. During manufacturing, extra devices may be inadvertently created. These extra devices are referred to as parasitic devices. The parasitic devices are not usually turned on during normal operation of the circuit, and current gain of parasitic pnp and npn bipolar transistors is normally very small.
However, in some circumstances, such as during a power-on period, the parasitic devices can be activated. This is because in an electronic system may include more than one level of power supply. During the power-on period, if a power supply with a lower voltage level comes on earlier than a power supply with a higher voltage level, a p-n junction could be forward biased. A parasitic pnp and npn, together, form a p-n-p-n thyristor. If the thyristor is connected between a power supply and an electrical ground, forward biasing of the p-n junction turns on the parasitic pnp and npn devices, which results in a high current flow from power supply to ground. A latch-up is a situation where the thyristor is triggered during the power-on period and causes a high current to flow from the power supply to ground. As a result of such high current, other circuits can be damaged, e.g., a melt down of metal wires. A detailed description of latch-up can be found in R. R. Troutman, “Latchup in CMOS Technology”, Kluwer Academic Publishers, Boston, 1986.
A CMOS circuit built on a bulk silicon wafer is susceptible to latch-up. When latch-up conditions are met, a low-impedance path, e.g., through p-n-p-n junctions, is established between a power supply and ground. Once latch-up occurs, not only may circuits cease to function, but the latch-up may also induce catastrophic failure from joule heating. Ordinarily, the latch-up cannot be stopped unless power is removed and the circuits are reactivated.
To power-on a system having multiple-voltage supplies, if one supply is ramped up faster (or slower) than another, it is possible that some p-n junctions may be unintentionally forward biased, and the system could enter the latch-up situation. A body of a MOS device is an area beneath a channel of the MOS device and between a source and drain of the device. A body of a p-type metal oxide semiconductor (PMOS) device is tied to a higher voltage level than that of the pMOS device's source/drain junctions. A guard ring is a diffusion ring that surrounds the pMOS device. The guard ring has an opposite doping polarity to that of the body, and is reverse biased to isolate the pMOS device. During power-on, if the higher voltage supply is ramped up more slowly than the lower voltage supply, a p-type source/drain junction may be forward biased to an n-type body, which could result in a latch-up, especially if guard rings are not installed.
A well is an isolated body region. In a CMOS circuit, in order to save silicon area, it is desirable to place all pMOS devices in a single n-well and to bias the n-well to a highest voltage level. Accordingly, the n-well is typically tied to a supply having a highest voltage level. If, instead of employing a single n-well, multiple n-wells are employed, then each of the multiple n-wells must be connected to a respective bias, and extra silicon area, as compared to a case of a single n-well, is required to accommodate well-to-well spacing.
However, in order to avoid latch-up, the sharing of wells is often prohibited. In a dynamic random access memory (DRAM), a higher voltage supply is generated from a lower voltage supply by using a charge pump and a voltage regulator. The higher voltage supply is inherently ramped up much latter than the lower voltage supply. DRAMs typically include a boost word supply line (Vpp) for boosting a voltage of a selected word line in order to achieve a proper access time for the selected word line. The boost word supply line Vpp is also typically the highest voltage level in the DRAM, for example, Vdd=1.5 volts and Vpp=3.0 volts. During a power-on sequence, after Vdd is ramped up, there is a delay of about 10 nanoseconds (ns) to 100 ns until the boost word line supply Vpp is ramped up. Since, in order to avoid latch-up, the sharing of wells is prohibited, a larger chip area is required than there would be if shared wells were permitted.